Invention Grant
US09379021B2 Method to reduce K value of dielectric layer for advanced FinFET formation
有权
降低先进FinFET形成介质层的K值的方法
- Patent Title: Method to reduce K value of dielectric layer for advanced FinFET formation
- Patent Title (中): 降低先进FinFET形成介质层的K值的方法
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Application No.: US14505167Application Date: 2014-10-02
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Publication No.: US09379021B2Publication Date: 2016-06-28
- Inventor: Ellie Y. Yieh , Ludovic Godet , Srinivas D. Nemani
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: B44C1/22
- IPC: B44C1/22 ; C03C15/00 ; C03C25/68 ; C23F1/00 ; H01L21/302 ; H01L21/461 ; H01L21/8234 ; H01L29/66 ; H01L21/28 ; H01L21/04 ; H01L21/225 ; H01L21/3115 ; H01L21/223
Abstract:
Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.
Public/Granted literature
- US20150099360A1 METHOD TO REDUCE K VALUE OF DIELECTRIC LAYER FOR ADVANCED FINFET FORMATION Public/Granted day:2015-04-09
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