Invention Grant
US09379719B1 Phase locked loop device 有权
锁相环装置

Phase locked loop device
Abstract:
A device is disclosed that includes a control module and a gain estimation module. The control module is configured to superimpose two non-zero values on a frequency control word to respectively generate a first and a second modified fractional reference phase signals, under a condition that a fractional part of the frequency control word is smaller than a predetermined value. The gain estimation module is configured to calculate a first and a second estimated gain values respectively based on the first and the second modified fractional reference phase signals. The control module is further configured to calculate an estimated digital-to-time converter gain value based on an interpolation of the first and the second estimated gain values.
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