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US09385074B2 Semiconductor package with embedded die 有权
半导体封装带嵌入式裸片

Semiconductor package with embedded die
Abstract:
A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.
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