Invention Grant
- Patent Title: Semiconductor package with embedded die
- Patent Title (中): 半导体封装带嵌入式裸片
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Application No.: US13935053Application Date: 2013-07-03
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Publication No.: US09385074B2Publication Date: 2016-07-05
- Inventor: Rajendra D. Pendse
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/31 ; H01L23/00 ; H01L25/10 ; H01L21/56

Abstract:
A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.
Public/Granted literature
- US20130292829A1 Semiconductor Package with Embedded Die Public/Granted day:2013-11-07
Information query
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