Invention Grant
- Patent Title: Interconnects with fully clad lines
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Application No.: US14855792Application Date: 2015-09-16
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Publication No.: US09385085B2Publication Date: 2016-07-05
- Inventor: Manish Chandhok , Hui Jae Yoo , Christopher J. Jezewski , Ramanan V. Chebiam , Colin T. Carver
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/532 ; H01L21/768 ; H01L23/522 ; H01L23/528

Abstract:
A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.
Public/Granted literature
- US20160005692A1 INTERCONNECTS WITH FULLY CLAD LINES Public/Granted day:2016-01-07
Information query
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