公开(公告)号：US12266568B2

公开(公告)日：2025-04-01

申请号：US18535623

申请日：2023-12-11

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US10553477B2

公开(公告)日：2020-02-04

申请号：US15773158

申请日：2015-12-04

Applicant: Aranzazu Maestre Caro ,  Ramanan V. Chebiam ,  Intel Corporation

Inventor： Aranzazu Maestre Caro ,  Ramanan V. Chebiam

IPC: H01L21/768 ,  H01L21/324 ,  C23C18/16 ,  B82Y30/00 ,  B82Y40/00

Abstract: Embodiments of the disclosure are directed to using a SAM liner to promote electroless deposition of metal for integrated circuit interconnects. The SAM liner can be formed on a dielectric substrate. A protective layer can be formed on the SAM liner. The protective layer can double as a seed layer for electroless deposition of an interconnect metal. The interconnect metal can be deposited on the protective layer using electroless deposition. The dielectric, with the SAM liner, the protective layer, and the interconnect metal can be annealed to reflow the interconnect metal into trenches formed in the dielectric.

公开(公告)号：US09165824B2

公开(公告)日：2015-10-20

申请号：US14039893

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Hui Jae Yoo ,  Christopher Jezewski ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

Abstract translation: 包括全覆层互连的金属化层和形成完全包层的互连的方法。 在电介质层中形成开口，其中介电层具有表面，并且开口包括壁和底部。 扩散阻挡层和粘合层沉积在介电层上。 互连材料沉积在介电层上并回流到形成互连的开口中。 在互连上沉积粘合覆盖层和扩散阻挡覆盖层。 互连被粘合层和粘合覆盖层包围，粘合层和粘合覆盖层被扩散阻挡层和扩散覆盖层包围。

公开(公告)号：US10700007B2

公开(公告)日：2020-06-30

申请号：US15925009

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US10068845B2

公开(公告)日：2018-09-04

申请号：US15126575

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Ramanan V. Chebiam ,  Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  James S. Clarke ,  John J. Plombon

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/321

Abstract: Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment, a method includes conformally depositing a metal into a recess disposed in a dielectric material to form an interconnect, wherein conformally depositing the metal creates a seam or void in the deposited metal within or directly adjacent to the recess and heating the metal in the presence of a reactive gas to remove the seam or void, wherein the metal has a melting point that is greater than a melting point of copper. Other embodiments may be described and/or claimed.

公开(公告)号：US09349636B2

公开(公告)日：2016-05-24

申请号：US14038502

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

Abstract translation: 介电层及其形成方法。 限定在介电层中的开口和沉积在开口内的电线，其中所述电线包括由护套材料围绕的芯材料，其中所述护套材料表现出第一电阻率1，并且所述芯材料表现出第二电阻率 和＆rgr; 2小于＆rgr; 1。

公开(公告)号：US10832951B2

公开(公告)日：2020-11-10

申请号：US15631701

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US09997457B2

公开(公告)日：2018-06-12

申请号：US14137526

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L23/53209 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/4966 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US09691657B2

公开(公告)日：2017-06-27

申请号：US15096609

申请日：2016-04-12

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US11881432B2

公开(公告)日：2024-01-23

申请号：US18088474

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L21/76843 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2224/45015 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.