Invention Grant
- Patent Title: Die interconnect
- Patent Title (中): 芯片互连
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Application No.: US14229717Application Date: 2014-03-28
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Publication No.: US09385099B2Publication Date: 2016-07-05
- Inventor: Leonardus Antonius Elisabeth van Gemert , Coenraad Cornelis Tak , Marten Oldsen , Hendrik Bouman
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP, B.V.
- Current Assignee: NXP, B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/66 ; H01L23/58 ; H01L23/00 ; B81B7/00
Abstract:
One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.
Public/Granted literature
- US20150279803A1 DIE INTERCONNECT Public/Granted day:2015-10-01
Information query
IPC分类:
