Invention Grant
- Patent Title: Memory devices including vertical pillars and methods of manufacturing and operating the same
- Patent Title (中): 存储器件包括垂直支柱及其制造和操作方法
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Application No.: US14529157Application Date: 2014-10-31
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Publication No.: US09385138B2Publication Date: 2016-07-05
- Inventor: Jae-Sung Sim , Jung-Dal Choi
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Muir Patent Law, PLLC
- Priority: KR10-2008-0054707 20080611
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L29/788 ; G11C16/04 ; G11C16/14 ; G11C16/26 ; H01L21/8234 ; H01L29/04 ; H01L29/16 ; H01L29/423 ; H01L29/66

Abstract:
In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.
Public/Granted literature
- US20150064865A1 MEMORY DEVICES INCLUDING VERTICAL PILLARS AND METHODS OF MANUFACTURING AND OPERATING THE SAME Public/Granted day:2015-03-05
Information query
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