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    Variable resistance memory devices
    2.
    发明授权
    Variable resistance memory devices 有权
    可变电阻存储器件

    公开(公告)号：US09391269B2

    公开(公告)日：2016-07-12

    申请号：US14457439

    申请日：2014-08-12

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jung-Moo Lee ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Jung-Dal Choi

    IPC分类号： H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L21/336 ,  H01L29/788 ,  H01L27/108

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1675

    摘要： A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

    摘要翻译： 可变电阻存储器件包括多个第一导线，多个第二导线，多个存储单元，多个第一气隙和多个第二气隙。 第一导线沿第一方向延伸。 第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。 存储单元包括可变电阻器件。 存储单元位于第一导线和第二导线的交叉区域。 第一气隙在存储单元之间沿第一方向延伸。 第二气隙沿第二方向在存储单元之间延伸。

    Nonvolatile memory devices
    4.
    发明授权
    Nonvolatile memory devices 有权
    非易失性存储器件

    公开(公告)号：US09184164B2

    公开(公告)日：2015-11-10

    申请号：US14134457

    申请日：2013-12-19

    申请人： Samsung Electronics Co., Ltd.

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi

    IPC分类号： H01L21/336 ,  H01L27/105 ,  H01L27/115 ,  G11C16/04

    CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

    摘要： A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

    摘要翻译： 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

    Method of programming a nonvolatile memory device
    5.
    发明授权
    Method of programming a nonvolatile memory device 有权
    非易失性存储器件编程方法

    公开(公告)号：US09159432B2

    公开(公告)日：2015-10-13

    申请号：US13790409

    申请日：2013-03-08

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Chang-Hyun Lee ,  Jee-Yeon Kang ,  Dong-Hoon Jang ,  Jung-Dal Choi

    IPC分类号： G11C16/24 ,  G11C16/04 ,  G11C16/10

    CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/10

    摘要： In method of programming a nonvolatile memory device including first and second cell strings that are coupled to one bitline, a first channel of the first cell string and a second channel of the second cell string are precharged by applying a first voltage to the bitline, one cell string is selected from the first and second cell strings, and a memory cell included in the selected cell string is programmed by applying a second voltage greater than a ground voltage and less than the first voltage to the bitline.

    摘要翻译： 在编程包括耦合到一个位线的第一和第二单元串的非易失性存储器件的方法中，通过向位线施加第一电压来预充电第一单元串的第一通道和第二单元串的第二通道，一个 从第一和第二单元串中选择单元串，并且通过向位线施加大于接地电压并小于第一电压的第二电压来对包括在所选单元串中的存储单元进行编程。

    Semiconductor devices and methods of manufacturing the same
    7.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权
    半导体器件及其制造方法

    公开(公告)号：US09202932B2

    公开(公告)日：2015-12-01

    申请号：US13834529

    申请日：2013-03-15

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seung-Woo Paek ,  Jung-Dal Choi ,  Young-Seop Rah ,  Byung-Kwan You ,  Seok-Won Lee

    IPC分类号： H01L21/3205 ,  H01L29/792 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/764 ,  H01L27/115 ,  H01L23/522

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/5222 ,  H01L27/11568 ,  H01L29/66833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.

    摘要翻译： 在制造半导体器件的方法中，可以在衬底上依次形成电介质层结构和控制栅极层。 可以部分蚀刻控制栅极层以形成多个控制栅极。 栅极间隔物和牺牲隔离物可以顺序地堆叠在控制栅极的侧壁上以及电介质层结构的一部分上。 可以使用牺牲间隔物和栅极间隔物作为蚀刻掩模来部分地蚀刻电介质层结构，以形成多个电介质层结构图案。 可以去除牺牲隔离物。 可以在基板上形成绝缘中间层以形成气隙。 绝缘中间层可以覆盖电介质层结构图案，栅极间隔物和控制栅极。 气隙可以在相邻的栅极间隔件之间和相邻的介电层结构图案之间延伸。

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20130094287A1

    公开(公告)日：2013-04-18

    申请号：US13652849

    申请日：2012-10-16

    申请人： Samsung Electronics Co. Ltd.

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Do-Hyun Lee

    IPC分类号： H01L29/788 ,  G11C16/06 ,  H01L21/336

    CPC分类号： G11C16/06 ,  G11C16/3418 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor device includes a bit line, a first cell string and a second cell string. The first cell string includes a first selecting transistor connected to the bit line in series and having a threshold voltage greater than a first reference voltage, a second selecting transistor having a threshold voltage smaller than a second reference voltage, cell transistors and a ground selecting transistor. The second cell string includes a third selecting transistor connected to the bit line in series and having a threshold voltage smaller than the first reference voltage, a fourth selecting transistor having a threshold voltage greater than the second reference voltage, cell transistors and a ground selecting transistor. A channel region of the first selecting transistor has an enhancement mode and a first conductive type. A channel region of the third selecting transistor has a depletion mode and a second conductive type.

    摘要翻译： 半导体器件包括位线，第一单元串和第二单元串。 第一单元串包括串联连接到位线并且具有大于第一参考电压的阈值电压的第一选择晶体管，具有小于第二参考电压的阈值电压的第二选择晶体管，单元晶体管和接地选择晶体管 。 第二单元串包括串联连接到位线并且具有小于第一参考电压的阈值电压的第三选择晶体管，具有大于第二参考电压的阈值电压的第四选择晶体管，单元晶体管和接地选择晶体管 。 第一选择晶体管的沟道区具有增强模式和第一导电类型。 第三选择晶体管的沟道区具有耗尽模式和第二导电类型。

    Fin field effect transistor, semiconductor device including the same and method of forming the semiconductor device
    10.
    发明授权
    Fin field effect transistor, semiconductor device including the same and method of forming the semiconductor device 有权
    鳍式场效应晶体管，包括其的半导体器件和形成半导体器件的方法

    公开(公告)号：US09391134B2

    公开(公告)日：2016-07-12

    申请号：US14336084

    申请日：2014-07-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： Chang-Jae Yang ,  Sang-Su Kim ,  Jae-Hwan Lee ,  Jung-Dal Choi

    IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

    CPC分类号： H01L29/06 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

    摘要： A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

    摘要翻译： 翅片场效应晶体管包括分别从第一和第二鳍结构上的衬底，第一和第二栅电极突出的第一鳍结构和第二鳍结构，以及在第一鳍和第二鳍结构中的每一个之间的栅极介电层 以及第一和第二栅电极。 第一和第二鳍结构中的每一个包括衬底上的缓冲图案，缓冲图案上的沟道图案，以及设置在沟道图案和衬底之间的蚀刻停止图案。 蚀刻停止图案包括具有大于缓冲图案的蚀刻电阻率的蚀刻电阻率的材料。