- 专利标题: Shallow trench isolation integration methods and devices formed thereby
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申请号: US14810167申请日: 2015-07-27
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公开(公告)号: US09385192B2公开(公告)日: 2016-07-05
- 发明人: Hongliang Shen , Kyutae Na , Sandeep Gaan , Hsin-Neng Tai , Weihua Tong , Sang Cheol Han , Tae Hoon Kim , Ja Hyung Han , Haigou Huang , Changyong Xiao , Huang Liu , Seung Yeon Kim
- 申请人: GLOBALFOUNDRIES Inc.
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人地址: KY Grand Cayman
- 代理机构: Williams Morgan, P.C.
- 主分类号: H01L21/762
- IPC分类号: H01L21/762 ; H01L29/06 ; H01L21/02 ; H01L27/088
摘要:
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.
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