Invention Grant
US09385708B2 Methodology to avoid gate stress for low voltage devices in FDSOI technology
有权
在FDSOI技术中避免低压器件栅极应力的方法
- Patent Title: Methodology to avoid gate stress for low voltage devices in FDSOI technology
- Patent Title (中): 在FDSOI技术中避免低压器件栅极应力的方法
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Application No.: US14216701Application Date: 2014-03-17
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Publication No.: US09385708B2Publication Date: 2016-07-05
- Inventor: Ankit Agrawal
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Seed IP Law Group PLLC
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/786 ; H03K3/00 ; H03K17/687 ; H03K17/10 ; H01L29/10 ; H01L29/423 ; H01L27/092
Abstract:
An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.
Public/Granted literature
- US20150263726A1 NOVEL METHODOLOGY TO AVOID GATE STRESS FOR LOW VOLTAGE DEVICES IN FDSOI TECHNOLOGY Public/Granted day:2015-09-17
Information query
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