Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.