Invention Grant
- Patent Title: Hierarchical write-combining cache coherence
- Patent Title (中): 分层写入组合高速缓存一致性
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Application No.: US14010096Application Date: 2013-08-26
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Publication No.: US09396112B2Publication Date: 2016-07-19
- Inventor: Blake A. Hechtman , Bradford M. Beckmann
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Volpe and Koenig, P.C.
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read-only cache and write-only combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events and reduces overhead in maintaining write-only combining buffers.
Public/Granted literature
- US20150058567A1 HIERARCHICAL WRITE-COMBINING CACHE COHERENCE Public/Granted day:2015-02-26
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