Invention Grant
- Patent Title: Methods for fabricating semiconductor devices using liner layers to avoid damage to underlying patterns
- Patent Title (中): 使用衬里层制造半导体器件以避免损坏底层图案的方法
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Application No.: US14703556Application Date: 2015-05-04
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Publication No.: US09396988B2Publication Date: 2016-07-19
- Inventor: Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
- Applicant: Kyoung-Woo Lee , Woo-Jin Lee , Jong-Sam Kim , Woo-Kyung You , Young-Sang Lee , Min Huh
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel & Sibley, PA
- Priority: KR10-2014-0122856 20140916
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/311 ; H01L21/70 ; H01L21/768

Abstract:
A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.
Public/Granted literature
- US20160079115A1 Methods for Fabricating Semiconductor Devices Using Liner Layers to Avoid Damage to Underlying Patterns Public/Granted day:2016-03-17
Information query
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