Invention Grant
US09401331B2 Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
有权
用于形成3-D FO-WLCSP的垂直互连结构的半导体器件和方法
- Patent Title: Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
- Patent Title (中): 用于形成3-D FO-WLCSP的垂直互连结构的半导体器件和方法
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Application No.: US14267800Application Date: 2014-05-01
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Publication No.: US09401331B2Publication Date: 2016-07-26
- Inventor: Yaojian Lin , Xusheng Bao , Kang Chen , Jianmin Fang
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/482
- IPC: H01L23/482 ; H01L23/538 ; H01L21/683 ; H01L25/065 ; H01L23/31 ; H01L23/00 ; H01L21/56

Abstract:
A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
Public/Granted literature
- US20140239495A1 Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP Public/Granted day:2014-08-28
Information query
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