发明授权
US09405719B2 Circuitry to generate and/or use at least one transmission time in at least one descriptor
有权
在至少一个描述符中生成和/或使用至少一个传输时间的电路
- 专利标题： Circuitry to generate and/or use at least one transmission time in at least one descriptor
- 专利标题（中）： 在至少一个描述符中生成和/或使用至少一个传输时间的电路
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申请号： US13993710申请日： 2011-11-11
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公开(公告)号： US09405719B2公开(公告)日： 2016-08-02
- 发明人: Reuven Rozic , Eric K. Mann
- 申请人： Reuven Rozic , Eric K. Mann
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Christopher K. Gagne
- 国际申请： PCT/US2011/060396 WO 20111111
- 国际公布： WO2013/070241 WO 20130516
- 主分类号： G06F13/42
- IPC分类号： G06F13/42 ; H04L12/815 ; H04L12/875 ; H04L12/801
摘要：
An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at least one descriptor may specify at least one transmission time at which the at least one packet is to be transmitted. The at least one transmission time may be specified in the at least one descriptor in such a manner as to permit the at least one transmission time to be explicitly identified based at least in part upon the at least one descriptor. Many alternatives, modifications, and variations are possible without departing from this embodiment.
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