High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.