Invention Grant
US09432015B2 Hysteresis comparator circuit having differential input transistors with switched bulk bias voltages 有权
迟滞比较器电路具有开关体积偏置电压的差分输入晶体管

Hysteresis comparator circuit having differential input transistors with switched bulk bias voltages
Abstract:
A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages.
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