Invention Grant
US09436605B2 Cache coherency apparatus and method minimizing memory writeback operations
有权
缓存一致性设备和最小化内存回写操作的方法
- Patent Title: Cache coherency apparatus and method minimizing memory writeback operations
- Patent Title (中): 缓存一致性设备和最小化内存回写操作的方法
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Application No.: US14136131Application Date: 2013-12-20
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Publication No.: US09436605B2Publication Date: 2016-09-06
- Inventor: Jeffrey D. Chamberlain , Vedaraman Geetha , Robert G. Blankenship , Yen-Cheng Liu , Adrian C. Moga , Herbert H. Hum , Sailesh Kottapalli
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.
Public/Granted literature
- US20150178206A1 CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OPERATIONS Public/Granted day:2015-06-25
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