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    Cache coherency apparatus and method minimizing memory writeback operations
    2.
    发明授权
    Cache coherency apparatus and method minimizing memory writeback operations 有权
    缓存一致性设备和最小化内存回写操作的方法

    公开(公告)号：US09436605B2

    公开(公告)日：2016-09-06

    申请号：US14136131

    申请日：2013-12-20

    Applicant: Intel Corporation

    Inventor： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

    IPC: G06F12/08

    CPC classification number: G06F12/0817 ,  G06F12/0815

    Abstract: An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

    Abstract translation: 一种用于减少或消除写回操作的设备和方法。 例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

    Synchronizing Multiple Threads Efficiently
    3.
    发明申请
    Synchronizing Multiple Threads Efficiently 审中-公开
    高效同步多线程

    公开(公告)号：US20140337857A1

    公开(公告)日：2014-11-13

    申请号：US14339763

    申请日：2014-07-24

    Applicant: Intel Corporation

    Inventor： Sailesh Kottapalli ,  John H. Crawford

    IPC: G06F9/52

    CPC classification number: G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

    Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

    Method and apparatus for store durability and ordering in a persistent memory architecture
    5.
    发明授权
    Method and apparatus for store durability and ordering in a persistent memory architecture 有权
    用于在持久存储器架构中存储耐久性和排序的方法和装置

    公开(公告)号：US09423959B2

    公开(公告)日：2016-08-23

    申请号：US13931875

    申请日：2013-06-29

    Applicant: Intel Corporation

    Inventor： Subramanya R. Dulloor ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Richard A. Uhlig ,  Robert S. Chappell ,  Joseph Nuzman ,  Kai Cheng ,  Sailesh Kottapalli ,  Yen-Cheng Liu ,  Mohan Kumar ,  Raj K. Ramanujan ,  Glenn J. Hinton

    IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

    CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

    Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

    Abstract translation: 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

    Synchronizing multiple threads efficiently
    6.
    发明授权
    Synchronizing multiple threads efficiently 有权
    有效地同步多个线程

    公开(公告)号：US08819684B2

    公开(公告)日：2014-08-26

    申请号：US13912777

    申请日：2013-06-07

    Applicant: Intel Corporation

    Inventor： Sailesh Kottapalli ,  John H. Crawford

    IPC: G06F9/46 ,  G06F12/00 ,  G06F12/08 ,  G06F9/52

    CPC classification number: G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

    Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

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