Invention Grant
- Patent Title: Semiconductor device and method of forming insulating layer around semiconductor die
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Application No.: US14449869Application Date: 2014-08-01
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Publication No.: US09437552B2Publication Date: 2016-09-06
- Inventor: Yaojian Lin , Kang Chen , Jianmin Fang , Xia Feng , Xusheng Bao
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L23/00 ; H01L23/28 ; H01L21/78 ; H01L23/29 ; H01L21/56 ; H01L23/538 ; H01L23/31 ; H01L23/498

Abstract:
A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
Public/Granted literature
- US20140339683A1 Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die Public/Granted day:2014-11-20
Information query
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