Invention Grant
- Patent Title: Multiple VT in III-V FETs
- Patent Title (中): III-V FET中的多个VT
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Application No.: US15057900Application Date: 2016-03-01
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Publication No.: US09437613B2Publication Date: 2016-09-06
- Inventor: Josephine B. Chang , Isaac Lauer , Amlan Majumdar , Jeffrey W. Sleight
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Kenneth R. Corsello
- Main IPC: H01L27/085
- IPC: H01L27/085 ; H01L27/092 ; H01L29/66 ; H01L29/778 ; H01L21/335 ; H01L27/12 ; H01L29/06 ; H01L29/205 ; H01L29/417 ; H01L29/08 ; H01L29/10

Abstract:
In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.
Public/Granted literature
- US20160181277A1 Multiple VT in III-V FETS Public/Granted day:2016-06-23
Information query
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