Invention Grant
- Patent Title: Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods
- Patent Title (中): 具有自对准接触工艺流程和制造方法中线路电容降低的集成电路
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Application No.: US14541754Application Date: 2014-11-14
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Publication No.: US09443944B2Publication Date: 2016-09-13
- Inventor: Hui Zang , Balasubramanian Pranatharthiharan
- Applicant: GLOBALFOUNDRIES Inc. , INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: KY Grand Cayman US NY Armonk
- Assignee: GLOBALFOUNDRIES INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: GLOBALFOUNDRIES INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: KY Grand Cayman US NY Armonk
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Agent Jacquelyn A. Graff
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/40 ; H01L21/28

Abstract:
Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are provided. One method includes, for instance: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes, for instance: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source; at least one second contact region positioned over a portion of the drain; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region.
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