Invention Grant
- Patent Title: Via structure and method thereof
- Patent Title (中): 其结构及其方法
-
Application No.: US14073307Application Date: 2013-11-06
-
Publication No.: US09448401B2Publication Date: 2016-09-20
- Inventor: Thorbjorn Ebefors , Edvard Kalvesten , Peter Agren , Niklas Svedin
- Applicant: SILEX Microsystems AB
- Applicant Address: SE Jarfalla
- Assignee: Silex Microsystems AB
- Current Assignee: Silex Microsystems AB
- Current Assignee Address: SE Jarfalla
- Agency: Pierce Atwood LLP
- Agent Kevin M. Farrell; David J. Wilson
- Priority: SE0802663 20081223
- Main IPC: G02B26/08
- IPC: G02B26/08 ; B81B7/00 ; H01L21/768 ; H01L23/48 ; G02B6/35

Abstract:
A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.
Public/Granted literature
- US20140063580A1 VIA STRUCTURE AND METHOD THEREOF Public/Granted day:2014-03-06
Information query