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    CTE MATCHED INTERPOSER AND METHOD OF MAKING
    2.
    发明申请
    CTE MATCHED INTERPOSER AND METHOD OF MAKING 有权
    CTE匹配插件及其制作方法

    公开(公告)号：US20150076677A1

    公开(公告)日：2015-03-19

    申请号：US14391855

    申请日：2013-04-15

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： Thorbjorn Ebefors ,  Daniel Perttu

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter,

    Abstract translation: 本插入器使得可以在非常宽的范围内调整插入件的热膨胀系数以使其附着的部件相匹配。 半导体插入器包括具有第一侧和相对的第二侧的半导体材料的衬底。 至少有一个导电晶圆通孔包括金属。 至少一个凹部设置在衬底的第一侧中，并且在衬底的半导体材料中，凹槽填充有金属并与晶片通孔连接，从而提供布线结构。 金属填充的通孔和金属填充的凹部的暴露表面基本上与衬底的第一侧上的衬底表面齐平。 晶圆通孔包括窄部分和较宽部分，并且接触元件设置在具有纵横比，高度：直径，<1：1，优选1：1至2：1的布线结构上。

    METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE
    3.
    发明申请
    METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE 有权
    提供通孔和路由结构的方法

    公开(公告)号：US20150054136A1

    公开(公告)日：2015-02-26

    申请号：US14389592

    申请日：2013-03-28

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： Thorbjorn Ebefors ,  Daniel Perttu

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76831 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is

    Abstract translation: 提供通孔和布线结构的方法包括：提供具有设置在晶片表面上的凹陷和盲孔的衬底晶片; 在凹槽和孔中提供绝缘层; 对孔和凹槽进行金属化; 并且去除孔的底部中的氧化物层以提供晶片的背侧和前侧之间的接触。 一种半导体器件，包括具有延伸穿过衬底的至少一个金属化通孔的衬底和形成与通孔一起布线的至少一个金属化凹槽。 前侧场和后侧场均有氧化层。 凹槽和通孔中的金属至少在前侧与场上的氧化物齐平，由此提供平坦的前侧。 半导体器件的厚度<300μm。

    Thin film capping
    4.
    发明授权
    Thin film capping 有权
    薄膜封盖

    公开(公告)号：US09511999B2

    公开(公告)日：2016-12-06

    申请号：US14365235

    申请日：2012-12-17

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： Thorbjorn Ebefors ,  Niklas Svedin

    IPC: H01L21/76 ,  B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145

    Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.

    Abstract translation: 一种用于在微电子/机械系统（MEMS）装置中密封空腔以在密封空腔内提供受控气氛的方法包括提供其上在基板的局部区域上提供模板的半导体衬底。 模板定义了腔的内部形状。 孔被制成以便能够排出空腔以提供期望的气氛以通过孔进入空腔。 最后，在孔中设置密封材料以密封空腔。 密封可以通过密封材料的压缩和/或熔化来制造。

    VIA STRUCTURE AND METHOD THEREOF
    5.
    发明申请
    VIA STRUCTURE AND METHOD THEREOF 有权
    通过其结构和方法

    公开(公告)号：US20140063580A1

    公开(公告)日：2014-03-06

    申请号：US14073307

    申请日：2013-11-06

    Applicant: SILEX Microsystems AB

    Inventor： Thorbjorn Ebefors ,  Edvard Kalvesten ,  Peter Agren ,  Niklas Svedin

    IPC: G02B26/08

    CPC classification number: G02B26/0833 ,  B81B7/0006 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  G02B6/3518 ,  G02B6/3584 ,  G02B26/0841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro- mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.

    Abstract translation: 分层微电子和/或微机械结构包括在导电层之间具有绝缘层的至少三个交替导电层。 还提供了在第一外层中的通孔，所述通孔包括由穿过该层的晶片天然材料制成的绝缘导电连接，在第一外层中延伸穿过其它层并进入所述通孔的导电插塞，以便提供 通过层的导电性，以及围绕所述其它层的至少一个所选层的所述导电插塞的绝缘外壳，用于使所述插塞与所述选定层中的材料绝缘。 它还涉及微电子和/或微机械装置，其包括设置在空腔上方的可动构件，使得其可在至少一个方向上移动。 该装置具有根据本发明的分层结构。 还提供了制造这种分层MEMS结构的方法。

    Via structure and method thereof
    6.
    发明授权
    Via structure and method thereof 有权
    其结构及其方法

    公开(公告)号：US09448401B2

    公开(公告)日：2016-09-20

    申请号：US14073307

    申请日：2013-11-06

    Applicant: SILEX Microsystems AB

    Inventor： Thorbjorn Ebefors ,  Edvard Kalvesten ,  Peter Agren ,  Niklas Svedin

    IPC: G02B26/08 ,  B81B7/00 ,  H01L21/768 ,  H01L23/48 ,  G02B6/35

    CPC classification number: G02B26/0833 ,  B81B7/0006 ,  B81B7/007 ,  B81B2207/092 ,  B81B2207/095 ,  G02B6/3518 ,  G02B6/3584 ,  G02B26/0841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.

    Abstract translation: 分层微电子和/或微机械结构包括在导电层之间具有绝缘层的至少三个交替导电层。 还提供了在第一外层中的通孔，所述通孔包括由穿过该层的晶片天然材料制成的绝缘导电连接，在第一外层中延伸穿过其它层并进入所述通孔的导电插塞，以便提供 通过层的导电性，以及围绕所述其它层的至少一个所选层的所述导电插塞的绝缘外壳，用于使所述插塞与所述选定层中的材料绝缘。 它还涉及微电子和/或微机械装置，其包括设置在空腔上方的可动构件，使得其可在至少一个方向上移动。 该装置具有根据本发明的分层结构。 还提供了制造这种分层MEMS结构的方法。

    ELECTROLESS METAL THROUGH SILICON VIA
    10.
    发明申请
    ELECTROLESS METAL THROUGH SILICON VIA 有权
    电绝缘金属通过硅

    公开(公告)号：US20150255344A1

    公开(公告)日：2015-09-10

    申请号：US14431002

    申请日：2013-09-27

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： Thorbjorn Ebefors ,  Henrik Knutsson

    IPC: H01L21/768

    CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/288 ,  H01L21/76847 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76888 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings

    Abstract translation: 在半导体衬底和衬底表面上的金属图案中制造具有高纵横比的衬底通过金属通孔的方法包括在衬底上提供半导体衬底（晶片）并沉积多晶硅。 衬底表面上的多晶硅通过蚀刻掉不需要的部分而被图案化。 然后，Ni通过无电解方法选择性地沉积在多晶硅上。 通孔穿过基底，其中孔中的壁经受与上述相同的处理。 Cu通过电镀工艺沉积在Ni上。 线宽度和间距<10μm位于晶片的两侧。

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