3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

Invention Grant

US09449913B2 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias 有权

Title translation: 3D互连结构包括与通过硅通孔组合的细间距单镶嵌背面金属再分配线

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Patent Title: 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
Patent Title (中): 3D互连结构包括与通过硅通孔组合的细间距单镶嵌背面金属再分配线
Application No.: US13994668

Application Date: 2011-10-28
Publication No.: US09449913B2

Publication Date: 2016-09-20
Inventor: Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
Applicant: Kevin J. Lee , Mark T. Bohr , Andrew W. Yeoh , Christopher M. Pelto , Hiten Kothari , Seshu V. Sattiraju , Hang-Shing Ma
Applicant Address: US CA Santa Clara
Assignee: Intel Corporation
Current Assignee: Intel Corporation
Current Assignee Address: US CA Santa Clara
Agency: Blakely, Sokoloff, Taylor & Zafman LLP
International Application: PCT/US2011/058429 WO 20111028
International Announcement: WO2013/062593 WO 20130502
Main IPC: H01L23/48
IPC: H01L23/48 ; H01L23/522 ; H01L21/768 ; H01L23/29 ; H01L23/00

3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

Abstract:

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Abstract(Chinese):

描述了三维互连结构和制造方法，其中金属再分配层（RDL）与硅通孔（TSV）集成并且使用单个镶嵌型工艺流程。氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

Public/Granted literature

US20130256910A1 3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH THROUGH-SILICON VIAS Public/Granted day:2013-10-03

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L23/00	半导体或其他固态器件的零部件（H01L25/00优先）
H01L23/48	.用于向或自处于工作中的固态物体通电的装置，例如引线或接线端装置