公开(公告)号：US20190259699A1

公开(公告)日：2019-08-22

申请号：US16348116

申请日：2016-12-23

Applicant: Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L21/306 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234

Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

公开(公告)号：US20140151817A1

公开(公告)日：2014-06-05

申请号：US14174822

申请日：2014-02-06

Applicant: Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Abstract translation: 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US20130285257A1

公开(公告)日：2013-10-31

申请号：US13994666

申请日：2011-10-28

Applicant: Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

Inventor： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5286 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/6835 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.

公开(公告)号：US08436404B2

公开(公告)日：2013-05-07

申请号：US12655408

申请日：2009-12-30

Applicant: Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US08013368B2

公开(公告)日：2011-09-06

申请号：US12288937

申请日：2008-10-24

Applicant: Mark T. Bohr

Inventor： Mark T. Bohr

IPC: H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11807 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Abstract translation: 本发明的一些实施例包括与NMOS和PMOS晶体管应变相关的装置和方法。

公开(公告)号：US07943468B2

公开(公告)日：2011-05-17

申请号：US12059455

申请日：2008-03-31

Applicant: Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

Inventor： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC: H01L21/336

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract translation: 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US20090242998A1

公开(公告)日：2009-10-01

申请号：US12059455

申请日：2008-03-31

Applicant: Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

Inventor： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract translation: 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US20090057772A1

公开(公告)日：2009-03-05

申请号：US12288937

申请日：2008-10-24

Applicant: Mark T. Bohr

Inventor： Mark T. Bohr

IPC: H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11807 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Abstract translation: 本发明的一些实施例包括与NMOS和PMOS晶体管应变相关的装置和方法。

公开(公告)号：US20080283906A1

公开(公告)日：2008-11-20

申请号：US11748376

申请日：2007-05-14

Applicant: Mark T. Bohr

Inventor： Mark T. Bohr

IPC: H01L29/778 ,  H01L21/336 ,  H01L29/76

CPC classification number: H01L29/7848 ,  H01L21/845 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7378 ,  H01L29/7834 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

Abstract translation: 描述了具有无衬底外延源极/漏极区域的半导体器件及其形成方法。 在一个实施例中，半导体器件包括在衬底上的栅极堆叠。 栅极堆叠由栅极电介质层上方的栅电极构成，并且位于衬底中的沟道区之上。 半导体器件还包括在沟道区两侧的衬底中的一对源/漏区。 该源极/漏极区域与栅极介质层直接接触，并且该源极/漏极区域的晶格常数不同于沟道区域的晶格常数。 在一个实施例中，半导体器件通过使用电介质栅叠层占位符形成。

公开(公告)号：US07208402B2

公开(公告)日：2007-04-24

申请号：US11144974

申请日：2005-06-03

Applicant: Mark T. Bohr ,  Robert W. Martell

Inventor： Mark T. Bohr ,  Robert W. Martell

IPC: H01L21/44 ,  H01L21/4763 ,  H01L29/40

CPC classification number: H01L24/02 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

Abstract translation: 一种装置，包括：具有顶部金属层的模具，所述顶部金属层由至少第一金属线和第二金属线构成; 覆盖顶部金属层的钝化层; 钝化层上的C4凸起; 以及钝化层中的第一钝化开口和第二钝化开口，用于将第一金属线连接到C4凸起的第一钝化开口，以及将第二金属线连接到C4凸起的第二钝化开口。