Invention Grant
US09450076B2 Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof
有权
具有降低导通电阻的功率LDMOS半导体器件及其制造方法
- Patent Title: Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof
- Patent Title (中): 具有降低导通电阻的功率LDMOS半导体器件及其制造方法
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Application No.: US14601081Application Date: 2015-01-20
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Publication No.: US09450076B2Publication Date: 2016-09-20
- Inventor: Salvatore Cascino , Leonardo Gervasi , Antonello Santangelo
- Applicant: STMICROELECTRONICS S.R.L.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed IP Law Group PLLC
- Priority: ITTO2014A0037 20140121
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/08 ; H01L29/417 ; H01L27/088

Abstract:
An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region.
Public/Granted literature
- US20150206968A1 POWER LDMOS SEMICONDUCTOR DEVICE WITH REDUCED ON-RESISTANCE AND MANUFACTURING METHOD THEREOF Public/Granted day:2015-07-23
Information query
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