Invention Grant
US09455013B2 System and method to trim reference levels in a resistive memory
有权
修改电阻式存储器中的参考电平的系统和方法
- Patent Title: System and method to trim reference levels in a resistive memory
- Patent Title (中): 修改电阻式存储器中的参考电平的系统和方法
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Application No.: US14992753Application Date: 2016-01-11
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Publication No.: US09455013B2Publication Date: 2016-09-27
- Inventor: Taehyun Kim , Jung Pill Kim , Sungryul Kim
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Toler Law Group, PC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; G11C13/00 ; G11C7/14 ; G11C11/15 ; G11C29/02

Abstract:
A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.
Public/Granted literature
- US20160125926A1 SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY Public/Granted day:2016-05-05
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