Invention Grant
- Patent Title: Multiple depth vias in an integrated circuit
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Application No.: US14949274Application Date: 2015-11-23
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Publication No.: US09455312B2Publication Date: 2016-09-27
- Inventor: Kaiping Liu , Imran Mahmood Khan , Richard Allen Faust
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L49/02 ; H01L23/48 ; H01L21/48 ; H01L23/522 ; H01L23/532 ; H01L21/768 ; H01L23/50 ; H01L21/02 ; H01L21/311
Abstract:
An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.
Public/Granted literature
- US20160079343A1 Multiple Depth Vias In an Integrated Circuit Public/Granted day:2016-03-17
Information query
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