Invention Grant
- Patent Title: Cascaded LUT carry logic circuit
- Patent Title (中): 级联LUT携带逻辑电路
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Application No.: US14851577Application Date: 2015-09-11
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Publication No.: US09455714B1Publication Date: 2016-09-27
- Inventor: Brian C. Gaide
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Robert M. Brush
- Main IPC: G06F15/00
- IPC: G06F15/00 ; H03K19/177

Abstract:
In an example, a configurable logic element for a programmable integrated circuit (IC) includes a first lookup-table (LUT) including first inputs and first outputs, and first sum logic and first carry logic coupled between the first inputs and the first outputs; a second LUT including second inputs and second outputs, and second sum logic coupled between the second inputs and the second outputs; and first and second cascade multiplexers respectively coupled to the first and second LUTs, an input of the second cascade multiplexer coupled to an output of the first carry logic in the first LUT.
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