公开(公告)号：US11868174B2

公开(公告)日：2024-01-09

申请号：US17127525

申请日：2020-12-18

Applicant: XILINX, INC.

Inventor： Brian C. Gaide

IPC: G06F1/10 ,  H01L23/00

CPC classification number: G06F1/10 ,  H01L24/02 ,  H01L2224/08145

Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.

公开(公告)号：US10825772B2

公开(公告)日：2020-11-03

申请号：US16571788

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Steven P. Young ,  Brian C. Gaide

IPC: H01L23/538 ,  H01L21/66 ,  H01L25/065

Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

公开(公告)号：US10741524B2

公开(公告)日：2020-08-11

申请号：US15967109

申请日：2018-04-30

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Matthew H. Klein

IPC: H01L25/065 ,  H01L23/535 ,  H01L21/66 ,  H01L25/00

Abstract: Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

公开(公告)号：US09496871B1

公开(公告)日：2016-11-15

申请号：US14462370

申请日：2014-08-18

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Brian C. Gaide ,  Santosh Kumar Sood

IPC: G11C5/14 ,  H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0016 ,  G11C5/063 ,  G11C5/147 ,  H03K19/17748

Abstract: An integrated circuit includes: a voltage rail; voltage control circuitry coupled to the voltage rail; and a circuit block coupled to the voltage control circuitry; wherein the voltage control circuitry is selectively configurable to operate the circuit block in at least a first mode of operation and a second mode of operation; wherein in the first mode of operation, the circuit block receives a voltage that is substantially the same as a voltage of the voltage rail; and wherein in the second mode of operation, the circuit block receives a voltage that is less than the voltage of the voltage rail by a threshold voltage.

Abstract translation: 集成电路包括：电压轨; 耦合到电压轨的电压控制电路; 以及耦合到所述电压控制电路的电路块; 其中所述电压控制电路被选择性地配置为在至少第一操作模式和第二操作模式中操作所述电路块; 其中在所述第一操作模式中，所述电路块接收与所述电压轨的电压基本相同的电压; 并且其中在所述第二操作模式中，所述电路块接收的电压小于所述电压轨的电压阈值电压。

公开(公告)号：US08893071B1

公开(公告)日：2014-11-18

申请号：US13941224

申请日：2013-07-12

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/84

Abstract: A method of pipelining a data path in an integrated circuit is described. The method comprises receiving a circuit design to be implemented in the integrated circuit device; providing a placement of the circuit design in the integrated circuit device; identifying a most critical path of the placement; adding pipeline registers to the most critical path; and adding pipeline registers to all paths that are parallel to the most critical path. A computer program product for pipelining a data path in an integrated circuit is also described.

Abstract translation: 描述了集成电路中的数据路径的流水线方法。 该方法包括接收要在集成电路装置中实现的电路设计; 提供电路设计在集成电路装置中的放置; 确定放置的最关键路径; 将流水线寄存器添加到最关键的路径; 并将流水线寄存器添加到与最关键路径并行的所有路径。 还描述了用于流水线集成电路中的数据路径的计算机程序产品。

公开(公告)号：US12261603B2

公开(公告)日：2025-03-25

申请号：US18320168

申请日：2023-05-18

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17704 ,  H03K19/17736

Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.

公开(公告)号：US11750195B2

公开(公告)日：2023-09-05

申请号：US17876456

申请日：2022-07-28

Applicant: XILINX, INC.

Inventor： Steven P. Young ,  Brian C. Gaide

IPC: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

CPC classification number: H03K19/17748 ,  G06F1/10 ,  G06F8/40 ,  H03K19/17736

Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

公开(公告)号：US11239203B2

公开(公告)日：2022-02-01

申请号：US16672077

申请日：2019-11-01

Applicant: XILINX, INC.

Inventor： Brian C. Gaide ,  Steven P. Young

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.

公开(公告)号：US20190181863A1

公开(公告)日：2019-06-13

申请号：US15836571

申请日：2017-12-08

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Brian C. Gaide ,  Henri Fraisse

IPC: H03K19/003 ,  H03K19/20 ,  H03K19/177 ,  H03K19/173 ,  H03K3/037 ,  H03K19/0175

Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

公开(公告)号：US10043724B1

公开(公告)日：2018-08-07

申请号：US15346179

申请日：2016-11-08

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Nui Chong

IPC: H01L23/10 ,  H01L27/118 ,  H01L21/78 ,  H01L23/538

Abstract: In an example, a semiconductor assembly includes an integrated circuit (IC) die. The IC die includes a first region that includes a programmable fabric; a second region that includes input/output (IO) circuits; and a third region that includes a die seal disposed between the programmable fabric and the IO circuits.