Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.