公开(公告)号：US11095216B2

公开(公告)日：2021-08-17

申请号：US14630506

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Yung-Chung Lo ,  Gang Zhang ,  Yiping Han ,  Frederic Bossu ,  Tsai-Pi Hung ,  Jae-Hong Chang

IPC: H02M3/156 ,  H02M1/00 ,  G05F1/575

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

公开(公告)号：US09455716B2

公开(公告)日：2016-09-27

申请号：US14488248

申请日：2014-09-16

Applicant: QUALCOMM Incorporated

Inventor： Hung-Chuan Pai ,  Gang Zhang

IPC: H03K21/02 ,  H04B1/40 ,  H03K5/133 ,  H03L7/081 ,  H03L7/16 ,  H03K23/66 ,  H03K5/00 ,  H03K5/13

CPC classification number: H03K21/02 ,  H03K5/00006 ,  H03K5/133 ,  H03K23/667 ,  H03L7/081 ,  H03L7/16 ,  H04B1/40

Abstract: Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.

Abstract translation: 提供可重构分频器电路的方面。 可重配置分频器可以包括被配置为接收输入信号的分频器。 分频器还可以包括被配置为接收由分频器产生的分频信号的延迟电路。 分频器还可以包括被配置为基于由延迟电路产生的延迟信号产生输出信号的倍频器，其中延迟电路被配置为接收输出信号。

公开(公告)号：US20140021988A1

公开(公告)日：2014-01-23

申请号：US14035870

申请日：2013-09-24

Applicant: QUALCOMM Incorporated

Inventor： Gang Zhang

IPC: H03L7/093

CPC classification number: H03L7/093 ,  H03H7/06 ,  H03H11/126 ,  H03L7/0893 ,  H03L2207/06

Abstract: A loop filter with noise cancellation includes first and second signal paths, an operational amplifier (op-amp), and a noise cancellation path. The first signal path provides a first transfer function (e.g., a lowpass response) for a first signal. The second signal path provides a second transfer function (e.g., an integration response) for a second signal. The second signal is a scaled version of, and smaller than, the first signal by a factor of alpha, where alpha is greater than one. A capacitor in the second signal path may be scaled smaller by a factor of alpha. The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal having op-amp noise. The noise cancellation path couples to the op-amp and provides a noise cancellation signal used to cancel the op-amp noise in the control signal.

Abstract translation: 具有噪声消除的环路滤波器包括第一和第二信号路径，运算放大器（运算放大器）和噪声消除路径。 第一信号路径为第一信号提供第一传递函数（例如，低通响应）。 第二信号路径为第二信号提供第二传递函数（例如，积分响应）。 第二信号是第一信号的缩放版本，并且小于第一信号乘以α的因子，其中α大于1。 第二信号路径中的电容器可以按比例缩小α的因子。 运算放大器耦合到第一和第二信号路径，并且有助于来自第一和第二信号路径的信号的相加，以产生具有运算放大器噪声的控制信号。 噪声消除路径耦合到运算放大器并且提供用于消除控制信号中的运算放大器噪声的噪声消除信号。

公开(公告)号：US11726513B2

公开(公告)日：2023-08-15

申请号：US17443093

申请日：2021-07-20

Applicant: QUALCOMM Incorporated

Inventor： Yung-Chung Lo ,  Gang Zhang ,  Yiping Han ,  Frederic Bossu ,  Tsai-Pi Hung ,  Jae-Hong Chang

IPC: G05F1/575 ,  H02M3/156 ,  H02M1/00

CPC classification number: G05F1/575 ,  H02M3/156 ,  H02M1/0077

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.