A system on chip (SoC) including a configurable image processing pipeline is provided. The SoC includes a bus; a first image processing module configured to be connected to the bus and to process image data; a first image processing stage configured to transmit either first image data or second image data received from the bus to at least one of the bus and the first image processing module through a first bypass path in response to first control signals; and a second image processing stage configured to transmit either third image data received from the first image processing module or fourth image data received from the bus to the bus through one of a second bypass path and a second scaler path in response to second control signals.