Invention Grant
US09461035B2 High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit
有权
高性能隔离垂直双极结型晶体管及其在CMOS集成电路中的形成方法
- Patent Title: High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit
- Patent Title (中): 高性能隔离垂直双极结型晶体管及其在CMOS集成电路中的形成方法
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Application No.: US14134312Application Date: 2013-12-19
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Publication No.: US09461035B2Publication Date: 2016-10-04
- Inventor: Derek W. Robinson , Amitava Chatterjee
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L21/8249 ; H01L29/66 ; H01L29/732 ; H01L29/10 ; H01L21/761 ; H01L21/762 ; H01L29/78
Abstract:
A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.
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