Invention Grant
US09461149B2 Nanowire structure with selected stack removed for reduced gate resistance and method of fabricating same
有权
选择的叠层的纳米线结构被去除以降低栅极电阻及其制造方法
- Patent Title: Nanowire structure with selected stack removed for reduced gate resistance and method of fabricating same
- Patent Title (中): 选择的叠层的纳米线结构被去除以降低栅极电阻及其制造方法
-
Application No.: US14484916Application Date: 2014-09-12
-
Publication No.: US09461149B2Publication Date: 2016-10-04
- Inventor: Hongmei Li , Junjun Li , Xiaoping Liang , Kai Zhao
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/66 ; H01L29/78

Abstract:
Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers.
Public/Granted literature
Information query
IPC分类: