公开(公告)号：US09620384B2

公开(公告)日：2017-04-11

申请号：US14323036

申请日：2014-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Claude Ortolland ,  Kai Zhao

IPC: H01L21/3115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L21/3115 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway.

公开(公告)号：US09461149B2

公开(公告)日：2016-10-04

申请号：US14484916

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongmei Li ,  Junjun Li ,  Xiaoping Liang ,  Kai Zhao

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers.

Abstract translation: 提供了制造具有降低的栅极电阻的堆叠的纳米线场效应晶体管（FET）的方法。 可以通过首先形成交替的牺牲材料层和纳米线材料层的材料堆叠来提供堆叠的纳米线FET中的纳米线堆叠。 随后去除材料堆叠中的牺牲材料层和选定的纳米线材料层以增加两个活性纳米线材料层之间的垂直距离。

公开(公告)号：US20200321332A1

公开(公告)日：2020-10-08

申请号：US16376234

申请日：2019-04-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Abu Naser M. Zainuddin ,  Christopher D. Sheraw ,  Sangameshwar Rao Saudari ,  Wei Ma ,  Kai Zhao ,  Bala S. Haran

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065

Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.

公开(公告)号：US10361132B2

公开(公告)日：2019-07-23

申请号：US15476158

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruqiang Bao ,  Takashi Ando ,  Aritra Dasgupta ,  Kai Zhao ,  Unoh Kwon ,  Siddarth A. Krishnan

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/285 ,  H01L21/311 ,  H01L27/092 ,  H01L21/8238

Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.

公开(公告)号：US09269786B2

公开(公告)日：2016-02-23

申请号：US14037423

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I-Chih Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Claude Ortolland ,  Kai Zhao

IPC: H01L29/76 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.

Abstract translation: 使用替代金属栅极（RMG）制造的标准高K金属栅极（HKMG）CMOS技术也被称为最终集成流，易受氧进入高K栅介质层和氧气扩散入栅极 电介质和半导体沟道区。 栅极电介质和半导体沟道界面处的氧会引起不必要的氧化物再生长，导致有效的氧化物厚度增加，并且晶体管阈值电压偏移，这两者都是高度可变的并且降低半导体芯片性能。 通过引入在低温下沉积的氮化硅，在金属栅极形成之后，可以避免氧进入和栅介质再生长，并且保持高的半导体芯片性能。