Invention Grant
US09466661B2 Method of fabricating a MIM capacitor with minimal voltage coefficient and a decoupling MIM capacitor and analog/RF MIM capacitor on the same chip with high-K dielectrics
有权
在具有高K电介质的同一芯片上制造具有最小电压系数的MIM电容器和解耦MIM电容器和模拟/ RF MIM电容器的方法
- Patent Title: Method of fabricating a MIM capacitor with minimal voltage coefficient and a decoupling MIM capacitor and analog/RF MIM capacitor on the same chip with high-K dielectrics
- Patent Title (中): 在具有高K电介质的同一芯片上制造具有最小电压系数的MIM电容器和解耦MIM电容器和模拟/ RF MIM电容器的方法
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Application No.: US14511746Application Date: 2014-10-10
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Publication No.: US09466661B2Publication Date: 2016-10-11
- Inventor: Dina Triyoso , Shao-Fu Sanford Chu , Bo Yu
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L27/08

Abstract:
Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient α; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient α′ opposite in polarity but substantially equal in magnitude to α; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.
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