Invention Grant
- Patent Title: Systems and methods of forming a reduced capacitance device
- Patent Title (中): 形成减电容器件的系统和方法
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Application No.: US14471086Application Date: 2014-08-28
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Publication No.: US09472453B2Publication Date: 2016-10-18
- Inventor: Jeffrey Junhao Xu , John Jianhong Zhu , Stanley Seungchul Song , Kern Rim , Choh Fei Yeap
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Toler Law Group, PC
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L21/311

Abstract:
A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.
Public/Granted literature
- US20150262875A1 SYSTEMS AND METHODS OF FORMING A REDUCED CAPACITANCE DEVICE Public/Granted day:2015-09-17
Information query
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