Invention Grant
US09472542B2 DRAM arrays, semiconductor constructions and DRAM array layouts
有权
DRAM阵列，半导体结构和DRAM阵列布局
- Patent Title: DRAM arrays, semiconductor constructions and DRAM array layouts
- Patent Title (中): DRAM阵列，半导体结构和DRAM阵列布局
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Application No.: US14024347Application Date: 2013-09-11
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Publication No.: US09472542B2Publication Date: 2016-10-18
- Inventor: Wolfgang Mueller , Sanh D. Tang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/336 ; H01L29/94 ; H01L27/108 ; H01L27/02 ; H01L29/423
Abstract:
Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. Cell active material structures are at intersections of the wordlines and bitlines. The cell active material structures have a first side coupled to a bitline and a second side coupled to a capacitor. The second side is on an opposite side of a wordline passing through a cell active material structure relative to the first side. Each cell active material structure has a connection to a bitline which is not shared with any other cell active material structures. Some embodiments include DRAM arrays and semiconductor constructions.
Public/Granted literature
- US20150069482A1 DRAM Arrays, Semiconductor Constructions and DRAM Array Layouts Public/Granted day:2015-03-12
Information query
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