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    DRAM arrays, semiconductor constructions and DRAM array layouts
    1.
    发明授权
    DRAM arrays, semiconductor constructions and DRAM array layouts 有权
    DRAM阵列，半导体结构和DRAM阵列布局

    公开(公告)号：US09472542B2

    公开(公告)日：2016-10-18

    申请号：US14024347

    申请日：2013-09-11

    申请人： Micron Technology, Inc.

    发明人： Wolfgang Mueller ,  Sanh D. Tang

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/94 ,  H01L27/108 ,  H01L27/02 ,  H01L29/423

    CPC分类号： H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/78

    摘要： Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. Cell active material structures are at intersections of the wordlines and bitlines. The cell active material structures have a first side coupled to a bitline and a second side coupled to a capacitor. The second side is on an opposite side of a wordline passing through a cell active material structure relative to the first side. Each cell active material structure has a connection to a bitline which is not shared with any other cell active material structures. Some embodiments include DRAM arrays and semiconductor constructions.

    摘要翻译： 一些实施例包括DRAM阵列布局。 字线沿着第一方向延伸，并且位线沿着穿过第一方向的第二方向延伸。 电池活性材料结构在字线和位线的交点处。 电池活性材料结构具有耦合到位线的第一侧和耦合到电容器的第二侧。 第二面位于相对于第一侧穿过细胞活性材料结构的字线的相反侧。 每个电池活性材料结构具有与不与任何其它电池活性材料结构共享的位线的连接。 一些实施例包括DRAM阵列和半导体结构。

    SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME 有权
    包括垂直存储器单元的半导体器件及其形成方法

    公开(公告)号：US20150129955A1

    公开(公告)日：2015-05-14

    申请号：US14075480

    申请日：2013-11-08

    申请人： Micron Technology, Inc.

    发明人： Wolfgang Mueller ,  Sanh D. Tang ,  Sourabh Dhir ,  Srinivas Pulugurtha

    IPC分类号： H01L29/78 ,  H01L27/105 ,  H01L29/66

    CPC分类号： H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

    摘要： A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.

    摘要翻译： 半导体器件可以包括存储器阵列，其包括连接到数字线，字线和主体连接线的垂直存储器单元。 存储器阵列的行或列可以包括连接到主体连接线的一个或多个支柱。 可以通过连接到主体连接线的至少一个支柱将电压施加到主体连接线。 施加电压到身体连接线可能会减少浮体效应。 公开了形成至少一个柱和电压源之间的连接的方法。 还公开了包括这种连接的半导体器件。

    DRAM Arrays, Semiconductor Constructions and DRAM Array Layouts
    6.
    发明申请
    DRAM Arrays, Semiconductor Constructions and DRAM Array Layouts 有权
    DRAM阵列，半导体构造和DRAM阵列布局

    公开(公告)号：US20150069482A1

    公开(公告)日：2015-03-12

    申请号：US14024347

    申请日：2013-09-11

    申请人： Micron Technology, Inc.

    发明人： Wolfgang Mueller ,  Sanh D. Tang

    IPC分类号： H01L27/108 ,  H01L27/02 ,  H01L29/78

    CPC分类号： H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/78

    摘要： Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. Cell active material structures are at intersections of the wordlines and bitlines. The cell active material structures have a first side coupled to a bitline and a second side coupled to a capacitor. The second side is on an opposite side of a wordline passing through a cell active material structure relative to the first side. Each cell active material structure has a connection to a bitline which is not shared with any other cell active material structures. Some embodiments include DRAM arrays and semiconductor constructions.

    摘要翻译： 一些实施例包括DRAM阵列布局。 字线沿着第一方向延伸，并且位线沿着穿过第一方向的第二方向延伸。 电池活性材料结构在字线和位线的交点处。 电池活性材料结构具有耦合到位线的第一侧和耦合到电容器的第二侧。 第二面位于相对于第一侧穿过细胞活性材料结构的字线的相反侧。 每个电池活性材料结构具有与不与任何其它电池活性材料结构共享的位线的连接。 一些实施例包括DRAM阵列和半导体结构。

    VERTICAL ACCESS DEVICE AND APPARATUSES HAVING A BODY CONNECTION LINE, AND RELATED METHOD OF OPERATING THE SAME
    8.
    发明申请
    VERTICAL ACCESS DEVICE AND APPARATUSES HAVING A BODY CONNECTION LINE, AND RELATED METHOD OF OPERATING THE SAME 有权
    具有身体连接线的垂直存取装置和装置及其相关操作方法

    公开(公告)号：US20140247674A1

    公开(公告)日：2014-09-04

    申请号：US13782792

    申请日：2013-03-01

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

    IPC分类号： H01L29/78 ,  G11C11/40

    CPC分类号： H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

    摘要： Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

    摘要翻译： 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。