Invention Grant
- Patent Title: Isolated semiconductor layer over buried isolation layer
- Patent Title (中): 隔离半导体层在掩埋隔离层上
-
Application No.: US14301848Application Date: 2014-06-11
-
Publication No.: US09472571B2Publication Date: 2016-10-18
- Inventor: Daniel Nelson Carothers , Jeffrey R. Debord
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L27/12 ; H01L21/762 ; H01L21/84 ; H01L21/02

Abstract:
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.
Public/Granted literature
- US20150294983A1 ISOLATED SEMICONDUCTOR LAYER OVER BURIED ISOLATION LAYER Public/Granted day:2015-10-15
Information query
IPC分类: