公开(公告)号：US10516019B2

公开(公告)日：2019-12-24

申请号：US16027522

申请日：2018-07-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/04 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/78

Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

公开(公告)号：US09818795B2

公开(公告)日：2017-11-14

申请号：US15255243

申请日：2016-09-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey R. Debord ,  Henry Litzmann Edwards ,  Kenneth J. Maggio

IPC: H01L29/66 ,  H01L27/16 ,  H01L35/04 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/06 ,  H01L23/485 ,  H01L23/522 ,  H01L35/30 ,  H01L27/092

CPC classification number: H01L27/16 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/0617 ,  H01L27/092 ,  H01L35/04 ,  H01L35/30 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In described examples, an integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

公开(公告)号：US09437652B2

公开(公告)日：2016-09-06

申请号：US14292281

申请日：2014-05-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey R. Debord ,  Henry Litzmann Edwards ,  Kenneth J. Maggio

IPC: H01L27/16 ,  H01L35/04 ,  H01L21/768 ,  H01L27/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/16 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/0617 ,  H01L27/092 ,  H01L35/04 ,  H01L35/30 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

Abstract translation: 可以通过形成有源区域来形成包含CMOS晶体管和嵌入式热电装置的集成电路，该有源区域为CMOS晶体管的NMOS晶体管和PMOS晶体管提供晶体管有源区，并提供n型热电元件和p型热电元件 嵌入式热电装置。 在n型热电元件和p型热电元件上形成横截面比大于4:1的拉伸接触，以通过金属互连提供到嵌入式热电器件的热节点的电连接和热连接。 拉伸接触通过在电介质层中形成接触沟槽，用接触金属填充接触沟槽并随后从电介质层上方去除接触金属而形成。 拉伸触点与NMOS和PMOS晶体管的触点同时形成。

公开(公告)号：US20180315816A1

公开(公告)日：2018-11-01

申请号：US16027522

申请日：2018-07-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC: H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/7851

Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

公开(公告)号：US20180096882A1

公开(公告)日：2018-04-05

申请号：US15831753

申请日：2017-12-05

Applicant: Texas Instruments Incorporated

Inventor： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02 ,  H01L21/306 ,  H01L21/84

CPC classification number: H01L21/76278 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76272 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/1203

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

公开(公告)号：US09472571B2

公开(公告)日：2016-10-18

申请号：US14301848

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC: H01L21/20 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L21/76278 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76272 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/1203

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

Abstract translation: 可以通过在单晶硅基衬底中形成隔离凹槽来形成集成电路。 侧壁绝缘体形成在隔离凹槽的侧壁上。 在隔离凹槽的底表面处形成热氧化物，以提供不会在侧壁绝缘体上延伸的掩埋隔离层。 在掩埋隔离层上形成单晶硅基半导体层，并平坦化以与邻近隔离凹槽的衬底基本共面，从而在掩埋隔离层上形成隔离的半导体层。 隔离的半导体层与衬底横向分离。

公开(公告)号：US20150294901A1

公开(公告)日：2015-10-15

申请号：US14301765

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC: H01L21/762 ,  H01L21/84 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/76267 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/76262 ,  H01L21/76281 ,  H01L21/84

Abstract: An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer.

Abstract translation: 通过在包括硅的单晶衬底中形成隔离凹槽来形成集成电路，用隔离电介质材料填充隔离凹槽，以及将隔离电介质材料平坦化以与衬底的顶表面共面以形成掩埋隔离层 。 非选择性外延工艺在衬底的暴露区域和掩埋隔离层上的多晶或非晶硅基材料上形成单晶硅基半导体材料。 在外延硅基材料上形成覆盖层，并且辐射诱导的再结晶过程使多晶或非晶硅基材料在掩埋隔离层上形成单晶半导体。

公开(公告)号：US10886164B2

公开(公告)日：2021-01-05

申请号：US15831753

申请日：2017-12-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC: H01L21/762 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L21/306

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

公开(公告)号：US20160379866A1

公开(公告)日：2016-12-29

申请号：US15263425

申请日：2016-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/76278 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76272 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/1203

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

Abstract translation: 可以通过在单晶硅基衬底中形成隔离凹槽来形成集成电路。 侧壁绝缘体形成在隔离凹槽的侧壁上。 在隔离凹槽的底表面处形成热氧化物，以提供不会在侧壁绝缘体上延伸的掩埋隔离层。 在掩埋隔离层上形成单晶硅基半导体层，并平坦化以与邻近隔离凹槽的衬底基本共面，从而在掩埋隔离层上形成隔离的半导体层。 隔离的半导体层与衬底横向分离。

公开(公告)号：US09496313B2

公开(公告)日：2016-11-15

申请号：US14292198

申请日：2014-05-30

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Toan Tran ,  Jeffrey R. Debord ,  Ashesh Parikh ,  Bradley David Sucher

IPC: H01L29/66 ,  H01L27/16 ,  H01L35/04 ,  H01L21/265 ,  H01L27/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/16 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L29/34 ,  H01L35/04 ,  H01L35/32 ,  H01L35/34

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between the CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract translation: 通过在CMOS晶体管之间和嵌入式热电元件的热电元件之间同时形成衬底中的隔离沟槽，形成包含CMOS晶体管和嵌入式热电元件的集成电路。 介电材料形成在隔离沟槽中，以提供横向隔离CMOS晶体管和热电元件的场氧化物。 在用于热电元件的区域中将锗植入衬底中，并且随后对衬底进行退火，以在隔离沟槽之间的热电元件中提供至少0.10原子％的锗密度。 在形成隔离沟槽之后，在形成隔离沟槽之后并且在隔离沟槽内形成电介质材料之前和/或在隔离沟槽中形成电介质材料之后，可以注入锗。