Invention Grant
- Patent Title: Barrier transactions in interconnects
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Application No.: US13960128Application Date: 2013-08-06
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Publication No.: US09477623B2Publication Date: 2016-10-25
- Inventor: Peter Andrew Riocreux , Bruce James Mathewson , Christopher William Laycock , Richard Roy Grisenthwaite
- Applicant: ARM LIMITED
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Priority: GB0917946.6 20091013; GB1007342.7 20100430
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F13/362 ; G06F13/364

Abstract:
Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.
Public/Granted literature
- US20140040516A1 BARRIER TRANSACTIONS IN INTERCONNECTS Public/Granted day:2014-02-06
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