A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclically samples a data signal to form sets of samples according to the in-phase, quadrature, and auxiliary clocks, each set comprising an in-phase sample, a quadrature sample, and an auxiliary sample. A CDR logic circuit processes the samples to form a timing word for each set.