公开(公告)号：US09584184B2

公开(公告)日：2017-02-28

申请号：US13784821

申请日：2013-03-05

申请人： QUALCOMM Incorporated

发明人： Miao Li ,  Xiaohua Kong ,  Jingcheng Zhuang ,  Wei Wang

IPC分类号： H04B1/06 ,  H04B7/00 ,  H04B3/50 ,  H04B3/30

CPC分类号： H04B3/50 ,  H04B3/30

摘要： Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.

摘要翻译： 这里描述了用于通过AC耦合或DC耦合在前端接收器处容纳输入信号的技术。 一方面，前端接收机包括具有第一数据线的差分输入和用于接收输入信号的第二数据线。 前端接收器还包括耦合到差分输入的AC耦合开关，其中AC耦合开关被配置为对输入信号执行高通滤波，并且通过DC偏移电压偏移滤波的输入信号，如果 接收器的AC耦合模式被使能。 前端接收器还包括耦合到差分输入的DC耦合开关，其中如果接收器的DC耦合模式被使能，则DC耦合开关被配置为移位输入信号的共模电压。

公开(公告)号：US20150280695A1

公开(公告)日：2015-10-01

申请号：US14228049

申请日：2014-03-27

申请人： QUALCOMM Incorporated

发明人： Miao Li ,  Xiaohua Kong ,  Zhi Zhu ,  Jie Xu

IPC分类号： H03K3/356

CPC分类号： H03K3/35613 ,  H03F3/45475 ,  H03F2200/291 ,  H03F2203/45081 ,  H03F2203/45084

摘要： A common mode voltage level shifting circuit including: input nodes configured to receive a differential signal with a first common mode voltage, a pair of shunt capacitors coupled between the input nodes and a corresponding pair of output nodes, a threshold voltage circuit, including the output nodes, coupled to the differential signal though the shunt capacitors, the threshold voltage circuit configured to provide a second common mode voltage for the differential signal at the output nodes, and current sources that are controlled according to a level of the first common mode voltage, the current sources coupled to the output nodes to effect the second common mode voltage.

摘要翻译： 一种共模电压电平移位电路，包括：被配置为接收具有第一共模电压的差分信号的输入节点，耦合在输入节点之间的一对并联电容器和相应的一对输出节点，包括输出端的阈值电压电路 节点，其通过并联电容器耦合到差分信号，阈值电压电路被配置为为输出节点处的差分信号提供第二共模电压，以及根据第一共模电压的电平来控制的电流源， 电流源耦合到输出节点以实现第二共模电压。

公开(公告)号：US08767841B1

公开(公告)日：2014-07-01

申请号：US13783751

申请日：2013-03-04

申请人： QUALCOMM Incorporated

发明人： Miao Li ,  Xiaohua Kong ,  Yan Hu ,  Zhi Zhu

IPC分类号： H04L25/00

CPC分类号： H04L25/0292 ,  H04L25/0276

摘要： Techniques for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver are described herein. In one embodiment, a method for receiving a signal comprises receiving the signal via a receiver input, the received signal comprising a differential signal and a common-mode clock signal. The method also comprises shifting the received signal from a first voltage range to a second voltage range that is lower than the first voltage range, and providing the shifted received signal on a first level-shifted signal line and a second level-shifted signal line. The method further comprises sensing voltage differences between the first and second level-shifted lines to recover the differential signal, and sensing common-mode voltages on the first and second level-shifted signal lines to recover the common-mode clock signal.

摘要翻译： 本文描述了用于对前端接收机中的高供应域差分信号和共模时钟进行解调的技术。 在一个实施例中，用于接收信号的方法包括经由接收器输入接收信号，所述接收信号包括差分信号和共模时钟信号。 该方法还包括将接收到的信号从第一电压范围移动到低于第一电压范围的第二电压范围，以及在第一电平移位信号线和第二电平移位信号线上提供移位的接收信号。 该方法还包括感测第一和第二电平移位线之间的电压差以恢复差分信号，以及感测第一和第二电平移位信号线上的共模电压以恢复共模时钟信号。

公开(公告)号：US20140176196A1

公开(公告)日：2014-06-26

申请号：US13725961

申请日：2012-12-21

申请人： QUALCOMM INCORPORATED

发明人： Miao Li ,  Madjid Hafizi ,  Xiaohua Kong

IPC分类号： G05F3/02 ,  H03K3/00

CPC分类号： G05F3/262 ,  H04L25/03847

摘要： A distribution current is split into a first control current, a second control current, and a third control current, in an apportionment according to a distribution command. A first control voltage is generated in response to the third control current. A second control voltage is generated as indication of the first control current, and a third control voltage is generated as indication of the second control current. Optionally, de-emphasis contribution of a first driver, a second driver and a third driver to an output is controlled based, at least in part, on the first control voltage, the second control voltage and the third control voltage, respectively.

摘要翻译： 根据分配命令，分配电流被分成第一控制电流，第二控制电流和第三控制电流。 响应于第三控制电流产生第一控制电压。 产生第二控制电压作为第一控制电流的指示，并且产生第三控制电压作为第二控制电流的指示。 可选地，至少部分地基于第一控制电压，第二控制电压和第三控制电压来控制第一驱动器，第二驱动器和第三驱动器对输出的去加重贡献。

公开(公告)号：US11863356B2

公开(公告)日：2024-01-02

申请号：US17589782

申请日：2022-01-31

申请人： QUALCOMM Incorporated

发明人： Miao Li ,  Zhiqin Chen ,  Yu Song ,  Hongmei Liao ,  Zhi Zhu ,  Hao Liu ,  Lejie Lu

IPC分类号： H04L25/03

CPC分类号： H04L25/03057 ,  H04L25/03885

摘要： A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

公开(公告)号：US11469730B2

公开(公告)日：2022-10-11

申请号：US17099183

申请日：2020-11-16

申请人： QUALCOMM Incorporated

发明人： Miao Li ,  Li Sun ,  Hao Liu

IPC分类号： H03F3/04 ,  H03G5/16 ,  H03G3/30 ,  H03F1/30

摘要： A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

公开(公告)号：US09264263B2

公开(公告)日：2016-02-16

申请号：US14257848

申请日：2014-04-21

申请人： QUALCOMM Incorporated

发明人： Madjid Hafizi ,  Xiaohua Kong ,  Zhi Zhu ,  Miao Li

IPC分类号： H04B3/00 ,  H04L25/02 ,  H04L7/00 ,  H03K5/12 ,  H03K19/0185

CPC分类号： H04L25/0276 ,  H03K5/12 ,  H03K19/018528 ,  H04L7/0091

摘要： A driver circuit for transmitting serial data on a communication link combines voltage-mode and current-mode drivers. The driver circuit uses a voltage-mode driver as the main output driver. One or more auxiliary current-mode drivers are connected in parallel with the voltage-mode driver to adjust the output signal by injecting currents into the outputs. The voltage-mode driver supplies most of the output drive. Thus, the output driver circuit can provide the power efficiency benefits associated with voltage-mode drivers. The current-mode drivers can provide, for example, pre-emphasis, level adjustment, skew compensation, and other modifications of the output signals. Thus, the driver circuit can also provide the signal adjustment abilities associated with current-mode drivers.

摘要翻译： 用于在通信链路上发送串行数据的驱动器电路组合电压模式和电流模式驱动器。 驱动电路使用电压模式驱动器作为主输出驱动器。 一个或多个辅助电流模式驱动器与电压模式驱动器并联连接，以通过向输出中注入电流来调整输出信号。 电压模式驱动器提供大部分输出驱动器。 因此，输出驱动器电路可以提供与电压模式驱动器相关联的功率效率益处。 电流模式驱动器可以提供例如预加重，电平调整，偏斜补偿和输出信号的其它修改。 因此，驱动器电路还可以提供与当前模式驱动器相关联的信号调节能力。

公开(公告)号：US09037437B2

公开(公告)日：2015-05-19

申请号：US14105213

申请日：2013-12-13

申请人： QUALCOMM Incorporated

发明人： Miao Li ,  Xiaohua Kong ,  Nam Van Dang ,  Cheng Zhong

IPC分类号： G06F11/30 ,  G01R31/3177 ,  G09G5/00 ,  G06F1/04

CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

公开(公告)号：US20140101507A1

公开(公告)日：2014-04-10

申请号：US14105213

申请日：2013-12-13

申请人： QUALCOMM INCORPORATED

发明人： Miao Li ,  Xiaohua Kong ,  Nam Van Dang ,  Cheng Zhong

IPC分类号： G01R31/3177 ,  G06F1/04

CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

公开(公告)号：US09485082B1

公开(公告)日：2016-11-01

申请号：US14747789

申请日：2015-06-23

申请人： QUALCOMM Incorporated

发明人： Li Sun ,  Zhi Zhu ,  Miao Li ,  Xiaohua Kong

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/0025 ,  H03L7/0807 ,  H04L7/033 ,  H04L7/0337

摘要： A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclically samples a data signal to form sets of samples according to the in-phase, quadrature, and auxiliary clocks, each set comprising an in-phase sample, a quadrature sample, and an auxiliary sample. A CDR logic circuit processes the samples to form a timing word for each set.

摘要翻译： 时钟和数据恢复（CDR）电路产生同相时钟，与同相时钟偏移90度的正交时钟，以及从同相时钟偏移90度的辅助时钟偏移。 数据采样器根据同相，正交和辅助时钟周期性地采样数据信号以形成采样组，每个组包括同相采样，正交采样和辅助采样。 CDR逻辑电路处理样本以形成每组的定时字。