Invention Grant
- Patent Title: Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process
- Patent Title (中): 在错误预测过程中预先计算直接分支部分目标地址的方法和装置
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Application No.: US13842835Application Date: 2013-03-15
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Publication No.: US09489204B2Publication Date: 2016-11-08
- Inventor: Jiajin Tu , Suresh K. Venkumahanti , Brian R. Mestan
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/32
Abstract:
An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.
Public/Granted literature
- US20140281440A1 PRECALCULATING THE DIRECT BRANCH PARTIAL TARGET ADDRESS DURING MISSPREDICTION CORRECTION PROCESS Public/Granted day:2014-09-18
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