公开(公告)号：US09489204B2

公开(公告)日：2016-11-08

申请号：US13842835

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Jiajin Tu ,  Suresh K. Venkumahanti ,  Brian R. Mestan

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3804 ,  G06F9/324 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3846 ,  G06F9/3861

Abstract: An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.

Abstract translation: 将部分目标地址存储在指令高速缓存中的示例性方法包括接收分支指令。 该方法还包括预测不采用分支指令的方向。 该方法还包括基于执行分支指令来计算目的地地址。 该方法还包括使用目的地址确定部分目标地址。 该方法还包括响应于从未被采取的转移指令的预测方向改变而取代指令高速缓存中的偏移与部分目标地址。

公开(公告)号：US20140281440A1

公开(公告)日：2014-09-18

申请号：US13842835

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Jiajin Tu ,  Suresh K. Venkumahanti ,  Brian R. Mestan

IPC: G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/324 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3846 ,  G06F9/3861

Abstract: An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.

Abstract translation: 将部分目标地址存储在指令高速缓存中的示例性方法包括接收分支指令。 该方法还包括预测不采用分支指令的方向。 该方法还包括基于执行分支指令来计算目的地地址。 该方法还包括使用目的地址确定部分目标地址。 该方法进一步包括响应于从未被采取的分支指令的预测方向改变，替换部分目标地址的指令高速缓存中的偏移。

公开(公告)号：US09858201B2

公开(公告)日：2018-01-02

申请号：US14626925

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Erich James Plondke ,  Jiajin Tu

IPC: G06F12/10 ,  G06F12/1027 ,  G06F11/07 ,  G06F12/08 ,  G06F1/32

CPC classification number: G06F12/1027 ,  G06F1/32 ,  G06F11/073 ,  G06F11/079 ,  G06F12/08 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/502 ,  G06F2212/684 ,  Y02D10/13

Abstract: A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

公开(公告)号：US09804969B2

公开(公告)日：2017-10-31

申请号：US13721442

申请日：2012-12-20

Applicant: QUALCOMM Incorporated

Inventor： Suresh K. Venkumahanti ,  Jiajin Tu ,  Phillip M. Jones

IPC: G06F12/1027 ,  G06F12/10 ,  G06F12/1009 ,  G06F9/38 ,  G06F12/1045

CPC classification number: G06F12/1027 ,  G06F9/3816 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1054 ,  G06F2212/654 ,  G06F2212/655

Abstract: A method includes receiving an instruction to be executed by a processor. The method further includes performing a lookup in a page crossing buffer that includes one or more entries to determine if the instruction has an entry in the page crossing buffer. Each of the entries includes a physical address. The method further includes, when the page crossing buffer has the entry in the page crossing buffer, retrieving a particular physical address from the entry in the page crossing buffer.

公开(公告)号：US09658793B2

公开(公告)日：2017-05-23

申请号：US14627433

申请日：2015-02-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Erich James Plondke ,  Jiajin Tu

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/08 ,  G06F12/1027 ,  G06F1/32 ,  G06F9/30 ,  G06F12/0888

CPC classification number: G06F3/0634 ,  G06F1/32 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/30076 ,  G06F12/08 ,  G06F12/0888 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/502 ,  Y02D10/13

Abstract: Processor access of memory is monitored. The monitoring includes identifying the accesses being to a local memory or a non-local memory. Based on the monitoring, the processor is switched from a non-local memory access mode to a local memory access mode.