Invention Grant
- Patent Title: Output buffer circuit with low sub-threshold leakage current
- Patent Title (中): 输出缓冲电路具有低次阈值漏电流
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Application No.: US14508943Application Date: 2014-10-07
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Publication No.: US09502083B2Publication Date: 2016-11-22
- Inventor: Tetsuya Arai , Yoshinori Matsui
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Priority: JP2013-209988 20131007
- Main IPC: G11C7/10
- IPC: G11C7/10 ; H03K17/687 ; G11C11/4096 ; G11C11/4093 ; G11C29/02 ; G11C29/50 ; G11C11/4074 ; G11C11/4076
Abstract:
A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive.
Public/Granted literature
- US20160078909A1 OUTPUT BUFFER CIRCUIT WITH LOW SUB-THRESHOLD LEAKAGE CURRENT Public/Granted day:2016-03-17
Information query
