Invention Grant
- Patent Title: Integrated circuit testing architecture
- Patent Title (中): 集成电路测试架构
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Application No.: US13843565Application Date: 2013-03-15
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Publication No.: US09506980B2Publication Date: 2016-11-29
- Inventor: Abram M. Detofsky , Brett D. Grossman , Jin Pan , John M. Peterson , Ronald K. Minemier
- Applicant: Abram M. Detofsky , Brett D. Grossman , Jin Pan , John M. Peterson , Ronald K. Minemier
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Konrad Raynes Davda & Victor LLP
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/28

Abstract:
In accordance with one aspect of the present description, an interface between an integrated circuit device and a test controller for testing the integrated circuit device includes a plurality of boards coupled together. In one embodiment, the test interface includes a plurality of interchangeable auxiliary boards, each having test circuitry, which may be coupled to a primary board and reused as appropriate to test various integrated circuits. Other aspects are described.
Public/Granted literature
- US20140266285A1 INTEGRATED CIRCUIT TESTING ARCHITECTURE Public/Granted day:2014-09-18
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